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Original author: 
Todd Hoff

It's not often you get so enthusiastic a recommendation for a paper as Sergio Bossa gives Memory Barriers: a Hardware View for Software Hackers: If you only want to read one piece about CPUs architecture, cache coherency and memory barriers, make it this one.

It is a clear and well written article. It even has a quiz. What's it about?

So what possessed CPU designers to cause them to inflict memory barriers on poor unsuspecting SMP software designers?

In short, because reordering memory references allows much better performance, and so memory barriers are needed to force ordering in things like synchronization primitives whose correct operation depends on ordered memory references.

Getting a more detailed answer to this question requires a good understanding of how CPU caches work, and especially what is required to make caches really work well. The following sections:

  1. present the structure of a cache,
  2. describe how cache-coherency protocols ensure that CPUs agree on the value of each location in memory, and, finally,
  3. outline how store buffers and invalidate queues help caches and cache-coherency protocols achieve high performance.

We will see that memory barriers are a necessary evil that is required to enable good performance and scalability, an evil that stems from the fact that CPUs are orders of magnitude faster than are both the interconnects between them and the memory they are attempting to access.

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Original author: 
Todd Hoff

When you have a large population of servers you have both the opportunity and the incentive to perform interesting studies. Authors from Google and the University of California in Optimizing Google’s Warehouse Scale Computers: The NUMA Experience conducted such a study, taking a look at how jobs run on clusters of machines using a NUMA architecture. Since NUMA is common on server class machines it's a topic of general interest for those looking to maximize machine utilization across clusters.

Some of the results are surprising:

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Original author: 
Sean Gallagher


The ArxCis-NV DIMM combines DDR3 dynamic memory with a flash memory backup.

Viking Technology

The server world still waits for DDR4, the next generation of dynamic memory, to be ready for prime time. In the meantime, a new set of memory boards from Viking is looking to squeeze more performance out of servers not by providing faster memory, but by making it safer to keep more in memory and less on disk or SSD. Viking Technology has begun supplying dual in-line memory modules that combine DDR3 dynamic memory with NAND flash memory to create non-volatile RAM for servers and storage arrays—modules that don't lose their memory when the systems they're in lose power or shut down.

The ArxCis-NV DIMM, which Viking demonstrated at the Storage Networking Industry Association's SNW Spring conference in Orlando this week, plugs into standard DIMM memory slots in servers and RAID controller cards.  Viking isn't the only player in the non-volatile DIMM game—Micron Technology and AgigA Tech announced their own NVDIMM effort in November—but they're first to market. The modules shipping now to a select group of server manufacturers have 4GB of dynamic RAM and 8GB of NAND memory. Modules with double those figures are planned for later in the year, and modules with 16GB of DRAM and 32GB of NAND are in the works for next year.

The ArxCis can be plugged into existing servers and RAID controllers today as a substitute for battery backed-up (BBU) memory modules. They are even equipped with batteries to power a last-gasp write to NAND memory in the event of a power outage. But the ArxCis is more than a better backup in the event of system failure. Viking's non-volatile DIMMs are primarily aimed at big in-memory computing tasks, such as high-speed in-memory transactional database systems and indices such as those used in search engines and other "hyper-scale" computing applications.  Facebook's "Unicorn" search engine system, for example, keeps massive indices in memory to allow for real-time response to user queries, as does the "type-ahead" feature in Google's search.

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New submitter jyujin writes "Ever wonder how long your SSD will last? It's funny how bad people are at estimating just how long '100,000 writes' are going to take when spread over a device that spans several thousand of those blocks over several gigabytes of memory. It obviously gets far worse with newer flash memory that is able to withstand a whopping million writes per cell. So yeah, let's crunch some numbers and fix that misconception. Spoiler: even at the maximum SATA 3.0 link speeds, you'd still find yourself waiting several months or even years for that SSD to start dying on you."

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An anonymous reader writes "Patrick Wyatt, one of the developers behind the original Warcraft and StarCraft games, as well as Diablo and Guild Wars, has a post about some of the bug hunting he's done throughout his career. He covers familiar topics — crunch time leading to stupid mistakes and finding bugs in compilers rather than game code — and shares a story about finding a way to diagnose hardware failure for players of Guild Wars. Quoting: '[Mike O'Brien] wrote a module ("OsStress") which would allocate a block of memory, perform calculations in that memory block, and then compare the results of the calculation to a table of known answers. He encoded this stress-test into the main game loop so that the computer would perform this verification step about 30-50 times per second. On a properly functioning computer this stress test should never fail, but surprisingly we discovered that on about 1% of the computers being used to play Guild Wars it did fail! One percent might not sound like a big deal, but when one million gamers play the game on any given day that means 10,000 would have at least one crash bug. Our programming team could spend weeks researching the bugs for just one day at that rate!'"

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