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Mark Cerny gives us our first look at the PS4's internals.

Andrew Cunningham

By the time Sony unveiled the PlayStation 4 at last night's press conference, the rumor mill had already basically told us what the console would be made of inside the (as-yet-nonexistent) box: an x86 processor and GPU from AMD and lots of memory.

Sony didn't reveal all of the specifics about its new console last night (and, indeed, the console itself was a notable no-show), but it did give us enough information to be able to draw some conclusions about just what the hardware can do. Let's talk about what components Sony is using, why it's using them, and what kind of performance we can expect from Sony's latest console when it ships this holiday season.

The CPU


AMD's Jaguar architecture, used for the PS4's eight CPU cores, is a follow-up to the company's Bobcat architecture for netbooks and low-power devices. AMD

We'll get started with the components of most interest to gamers: the chip that actually pushes all those polygons.

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First time accepted submitter thrae writes "Adapteva has just released the architecture and software reference manuals for their many-core Epiphany processors. Adapteva's goal is to bring massively parallel programming to the masses with a sub-$100 16-core system and a sub-$200 64-core system. The architecture has advantages over GPUs in terms of future scaling and ease of use. Adapteva is planning to make the products open source. Ars Technica has a nice overview of the project."


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Intel has been working on its "Many Integrated Core" architecture for a quite some time, but the chipmaker has finally taken the code-name gloves off and announced that Knights Corner will be the first in a new family of Xeon processors — the Xeon Phi. These co-processors will debut later this year (Intel says "by the end of 2012"), and will come in the form of a 50-core PCIe card that includes at least 8GB of GDDR5 RAM. The card runs an independent Linux operating system that manages each x86 core, and Intel is hoping that giving developers a familiar architecture to program for will make the Xeon Phi a much more attractive platform than Nvidia's Tesla.

The Phi is part of Intel's High Performance Computing (HPC) program, where the...

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Re-Configurable EXASCALE Computing

Google Tech Talk February 15, 2011 Presented by Steven J Wallach, Convey Computer Corp. ABSTRACT HPC research is focused on achieving ExaFlop/ExaOP performance by 2020. Unlike reaching a PetaFlop, the general consensus is that vastly new programming paradigms, hardware architectures, and interconnects will be needed (as well as new power plants). This presentation will be focused on increasing uni-processor performance and the roles played by application specific heterogeneous computing and compilers in evolving processor architecture. Steven J Wallach is a founder of Convey Computer Corporation and is an adviser to venture capital firms CenterPoint Ventures, Sevin-Rosen and InterWest Partners. Previously, he served as vice president of technology for Chiaro Networks Ltd., and as co-founder, chief technology officer and senior vice president of development of Convex Computer Corporation. After Hewlett-Packard Co. bought Convex, Wallach became chief technology officer of HP's Enterprise Systems Group. Wallach served as a consultant to the US Department of Energy's Advanced Simulation and Computing Program at Los Alamos National Laboratory from 1998 to 2007. He was also a visiting professor at Rice University in 1998 and 1999, and was manager of advanced development for Data General Corporation. His efforts on the MV/8000 are chronicled in Tracy Kidder's Pulitzer Prize winning book, "The Soul of a New Machine." Wallach, who has 34 patents, is a member of the National <b>...</b>
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